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6.6.2 Interrupt Mask Modes and Pin Polarity
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register even if the interrupt itself is masked.
However, in that case no timing information for this interrupt is provided. The Table
6-11 , Figure 6-21 , and Figure 6-22 describes the function.
Table 6-11. IRQ Mask Configuration.
IRQ_MASK Value
0
0
≠ 0
≠ 0
IRQ_MASK_MODE
0
1
0
1
Description
IRQ is suppressed entirely and none of interrupt
causes are shown in register IRQ_STATUS.
IRQ is suppressed entirely but all interrupt
causes are shown in register IRQ_STATUS.
All enabled interrupts are signaled on IRQ pin
and are also shown in register IRQ_STATUS.
All enabled interrupts are signaled on IRQ pin
and all interrupt causes are shown in register
IRQ_STATUS.
Figure 6-21. IRQ_MASK_MODE = 0.
.
.
.
IRQ_MASK
(register 0x0E)
IRQ_STATUS
(register 0x0F)
OR
IRQ
Figure 6-22. IRQ_MASK_MODE = 1.
.
.
.
IRQ_STATUS
(register 0x0F)
IRQ_MASK
(register 0x0E)
OR
IRQ
The Atmel AT86RF232 IRQ pin polarity can be configured with register bit
IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high,
which means that pin 24 (IRQ) = H issues an interrupt request.
If “Frame Buffer Empty Indicator ” is enabled during Frame Buffer read access the IRQ
pin has an alternative functionality, refer to Section 11.5 for details.
26
AT86RF232
8321A – MCU Wireless – 10/11
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